The present invention relates to a semiconductor memory array, and more specifically, to the semiconductor memory array having a bit line structure capable of increasing the pitch between the bit lines.
In general, a semiconductor memory device includes a plurality of bit lines, a plurality of sense amplifiers, a plurality of word lines, and a plurality of memory cells. However, as the semiconductor memory device tends to have higher packing cells, the pitch between the respective lines is decreased.
In other words, when the pitch between the bit lines is decreased, the pitch between the sense amplifiers is also decreased, and then a layout of the sense amplifiers is difficult.
At this time, miniaturization of a semiconductor memory device makes fabrication of the semiconductor memory device complicated and difficult because of the elaborate pattern of the semiconductor memory device.
In FIG. 1, a conventional memory cell array, pairs of bit lines are connected to each sense amplifier. Referring to FIG. 1, as the number of the sense amplifiers is proportional to how large the capacity of the memory is, parasitic capacitance in the connections between the bit lines and lines from the sense amplifiers increases in accordance with an increase of the capacity of the memory. The increase of the parasitic capacitance causes the operational speed of the sense amplifiers to be slower, so that the access time is delayed.